FIG. 1 depicts an exemplary flash memory cell 100 during an erase operating condition. A memory field may comprise HS3P (Hot Source Triple Poly) memory cells, organized in rows and columns To erase the cell, a strong electric field from a well 101 to a control gate (CG) 102 is employed to initiate Fowler-Nordheim tunneling of electrons from a floating gate (FG) 104 to the well 101. A select gate (SG) 103 is kept at an intermediate voltage to evenly distribute the electric stress to the two oxides of the spacer poly. A bitline (BL) 105 is floating, whereas a source line (SL) 106 is at the same potential as the well 101.
In the example according to FIG. 1, the well 101 and the source line (SL) 106 are at 14V, −5V is applied to the control gate (CG) 102, and 6V is supplied to the select gate (SG) 103.
FIG. 2 shows a memory field 200 during an exemplary erase condition. In this example, a page 201 is selected via the control gate (CG) 102, wherein the memory cell 100 according to FIG. 1 is located within the page 201. Erasing the page 201 by an erase pulse has an impact on electrically coupled memory cells, e.g., a page 202 to which a voltage amounting to 9.5V is applied via a control gate (CG) 203.
Typically, blocks of cells are erased simultaneously, such as a complete row or a group of rows in an array (in FIG. 2 shown as page 201), for example. After such a block erase, not all cells of the block have exactly the same threshold voltage, but have a normal distribution of threshold voltages due to the variations between cells.
A single erase pulse can be used to erase the memory cell 100, but with a trade-off between a cycling endurance and a disturbance of other memory cells or pages of the semiconductor device.
One problem associated with non-volatile memories, e.g., EEPROMs (Electrically Erasable Programmable Read-Only Memories), is that after repeated programming cycles (i.e. writing and erasing), there is a change in the programming behavior of the cells (i.e. the write behavior and the erase behavior). This change is normally caused by an accumulation of trapped charges in proximity to the floating gate which can affect either the reading of the cell and/or the electron tunneling characteristics during writing and erasing. Such effects can be referred to as endurance or cycling degradation. Over time, the accumulation of trapped charges from such cycling changes the threshold voltage distribution of the blocks of cells being in the erased state. Generally, cycling degradation causes an increase in the threshold voltages over time. Eventually, the erase threshold voltage of some cells may be increased to a level that causes errors and therefore limits the allowable number of cycles of the memory.